An international team from Milan Polytechnic, Italy and Micron, Boise Idaho provided an update on the their work using RRAMs for unsupervised learning. Unsupervised learning is the ability to learn and recognize random patterns. Supervised learning would be learning the images of say traffic lights and hand writing.
The team offered solutions for spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP) with a RRAM at the core of each circuit solution.
Late last year at IEDM-2016 Toshiba with Hynix announced plans for a 4Gbit MRAM and even although perhaps 3 to 4 years away from a commercial and proven product, plus the progress made by other MRAM vendors must be read as danger signals for PCM/RRAM product developers. It may be time for the PCM and RRAM communities to look at brain-gates as a potentially more rewarding future direction where their technologies will be able to offer unique features. Brain-gate: a circuit or array where the unique features of PCM/RRAM are integrated with conventional silicon.
Source: Ron Neale
Neural networks with resistive-switching memory (RRAM) synapses can mimic learning and recognition in the human brain, thus overcoming the major limitations of von Neumann computing architectures. While most researchers aim at supervised learning of a pre-determined set of patterns, unsupervised learning of patterns might be attractive for brain-inspired robot/drone navigation. Here we demonstrate neural networks with CMOS/RRAM synapses capable of unsupervised learning by spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP). First, STDP learning in a RRAM synaptic network is demonstrated. Then we present a 4-transistor/1-resistor synapse capable of SRDP, finally demonstrating SRDP learning, update, and recognition of patterns at the level of neural network.
We demonstrate a solid-state spiking artificial neuron based upon an insulator-to-metal (IMT) transition material element that operates at an unprecedented low voltage (0.8 V). We have developed a general coupled electrical-thermal device model for IMT based devices to accurately predict experimental outcomes. From the experiment and simulation, we show that voltage scalability to sub 0.3 V is possible by scaling of the IMT based neuron.
SOURCES – EEtimes, IEEE Electron Devices Meeting
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