Lam Research Corporation is a $17 billion wafer-fabrication equipment maker. They are simulating and designing next generation computer memory. Its products are used primarily in front-end wafer processing, which involves the steps that create the active components of semiconductor devices and their wiring.
They expect the semiconductor industry to evolve from 2D to 3D DRAM over the next five to eight years based on current technical capabilities. Next generation memory is starting today with planning and architectural design.
Lam is simulating DRAM’s untested future by creating proposals for what 3D DRAM architecture could look like. They are using SEMulator3D® computer software, which is typically used to virtually fabricate devices by mimicking wafer fabrication. Here are some suggestions for a 3D DRAM architecture, addressing:
Scaling issues
Stacking challenges
Shrinking footprints
Innovative connections
Via arrays
Process requirements
The plans is to till halve the volume needed for computer memory every 6-7 years.
Today (D1z on the chart above), the area per bit is at about 20.4E-4 µm2. Soon, driving higher density of bits (i.e., further reduction of the area per bit) by reducing the footprint of the capacitors by making them taller will not be possible because etch and deposition processes for capacitor fabrication cannot handle the extreme (high) aspect ratio.
On the chart above, our industry is expected to be able to maintain 2D DRAM until reaching ~10.4E-4 µm2 area per bit, which is about five years out. After that the lack of space becomes a problem that will likely demand going vertical—3D DRAM.
Reimagined Architecture
Lam’s designers using hte Lam’s SEMulator3D have proposed several changes to provide more space for capacitor processing while reducing the silicon area, thereby shrinking the nanosheets’ footprint.
They moved the bitline (BL) to the opposite side of the nanosheet, so the current will travel through the entire nanosheet through the transistor gate. The effect overall increases space for capacitor processing and also reduces the silicon area’s footprint. A DRAM structure is composed of a conductive material/structure called a bitline, which provides the carriers (current) to be injected into a transistor.
Second, they introduced gate-all-around transistors to further reduce the silicon active area. They also made the capacitors—once skinny and tall—short and wide. This is possible because of the space gained by moving the BL to the center of the architecture.
Finally, they increased the quantity of transistors/capacitors per bitline contact (no reason to be limited to two transistors per bitline) by placing transistors/capacitors on both sides of the bitline contact. This reconfigured nanosheet (as seen from a top-down view above) can then be stacked (as seen below).
The first iteration of a stacked 3D DRAM would be 28 layers tall (above) and would be two nodes (~13E-4 µm2 per bit) ahead of D1z today. The more layers, of course, the more bits we have and therefore, the greater the density.
The key components of a 28-layer 3D nanosheet include:
A stack of gate-all-around nanosheet silicon transistors
A stack of bitline layers in between two rows of transistors
24 vertical wordlines
Multibridge connections between bitline layers and transistors; transistors and capacitors
An array of horizontal MIM (metal-isolation-mental) capacitors
Making the Via Array
To avoid the limitations of staircase construction used in 3D NAND, Lam proposes putting the contact inside the memory cell by introducing an array of vias that goes through the silicon stack and can stop at each level—one via per level. Once the trenches are made, they introduce an isolation spacer that’s only on the side wall.
The tall trenches are used to introduce etching medium to remove silicon and then to introduce conductive metal in the empty trenches. The result is that each square on the top (the light green and purple boxes in the last three images below) connects to only one layer below.
They are working on all the process and manufactuing steps.
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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I would like to see LAM design a 3D SRAM memory. Serebras has shown that you can make fantastically efficient ANN training computers with SRAM and wafer scale computing. The weakest “link” in their design is their relatively small size of SRAM. Imagine having 20 times more SRAM on the same computing die…
If that were done it would probably be done by wafer bonding a 3D memory wafer with a logic wafer similarly to how. It wouldn’t male sense to combine such highly different processes all on a single wafer.
LAM is a serious company, and it is great they think they have found a way to continue shrinking density. One thing I don’t understand is why no one addresses the elephant in the room with these dense 3D structure i.e. how to dissipate the heat from operation?