Nature Nanotechnology – Nanopores could potentially be used to perform single-molecule DNA sequencing at low cost and with high throughput. Although single base resolution and differentiation have been demonstrated with nanopores using ionic current measurements direct sequencing has not been achieved because of the difficulties in recording very small (~pA) ionic currents at a bandwidth consistent with fast translocation speeds. Here, we show that solid-state nanopores can be combined with silicon nanowire field-effect transistors to create sensors in which detection is localized and self-aligned at the nanopore. Well-defined field-effect transistor signals associated with DNA translocation are recorded when an ionic strength gradient is imposed across the nanopores. Measurements and modelling show that field-effect transistor signals are generated by highly localized changes in the electrical potential during DNA translocation, and that nanowire–nanopore sensors could enable large-scale integration with a high intrinsic bandwidth.
Images of representative devices. a. Low resolution TEM image of the central SiNx membrane part of a nanowire-nanopore chip. Scale bar = 20 μm. The central bright rectangle is the suspended SiNx membrane area with nanowire-nanopore FETs. Dark lines on the membrane are metal contacts. Yellow arrows point to the source and drain contact of a nanowire-nanopore FET (not visible in gap between two contacts). b. Optical image of the device side of the SiNx membrane chip. Image size = 1.6 mm × 1.6 mm. The central bright rectangle is the suspended SiNx membrane and bright stripes are metal lines connecting FET to the large metal wirebonding pads visible on the edges of this image. c. Photograph of a home-made PCB chip carrier with a SiNx membrane chip glued on. PCB board size = 4 cm × 4 cm. The central dark part is the SiNx membrane chip. Bright metal lines on the chip carrier are copper, which are used to interface the devices to outside instrumentation. A few wire bonding wires are visible between the chip and copper lines. d. Photograph of a PCB chip carrier with assembled PDMS chambers.