Could 3d chip technology extend Moore’s law to 2030?

Most experts believe that silicon scaling will end by 2020 at the 10 nanometer node. Although several promising post-CMOS technologies, such as graphene or III-V compound semiconductors or even spintronics might take its place, these technologies will not be deployed before 2025 at the earliest. But if the industry were to adopt and perfect 3d technology, the industry might eventually create chips with hundreds of layers. The most common form of 3d technology involves through silicon vias, but a startup company called Monolithic 3d has an alternate approach. In an interview with Sander Olson for Next Big Future, Monolithic CEO Zvi Or-Bach argues that monolithic 3d is a viable, cost-effective technology that could keep Moore’s law going until 2030.

Zvi Or-Bach

Question: You founded Monolithic 3D logic in 2009 as NuPGA, with a focus on Field-Programmable-Gate-Arrays (FPGAs). What made you change the focus to monolithic 3D IC?

We originally were going to make a better FPGA technology, but in the development effort we discovered a path for monolithic 3D ICs. As soon as I realized the enormous potential of monolithic 3D, I told my staff to forget about FPGAs and concentrate exclusively on monolithic 3D IC. Monolithic 3D integration was investigated back in the 1980s, but no practical path was found due to limitation of maximum processing temperature of 400 ÂșC after interconnection layers had been processed in. MonolithIC 3D Inc. discovered and invented multiple process flow for monolithic 3D IC, and now that 2D scaling is reaching some fundamental limits, the semiconductor industry is rediscovering the compelling benefits of 3D.

Question: How long will conventional 2D scaling continue?

From now on, every processor node will require new materials and structures, since “classic” semiconductor scaling is no longer adequate. The 2012 book Chips 2020 predicts that traditional 2D scaling will end by 2020, even with Herculean efforts by Intel and others. At that point features will be 10 nanometers, which is probably the practical limit of miniaturization. Even getting to 10 nm will be quite expensive, requiring multi-billion dollar fabs and similar R&D investments. Chip design R&D is also continually rising. But by using monolithic 3D, we can extend Moore’s law going until 2030.

Extreme Tech – Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless, International Trade Partner Conference (ITPC) forum Nov. 2011

Question: How does monolithic 3D help with the “interconnect problem”?

Computer chips require switching transistors, and interconnects, or wiring. Unlike transistors, which generally perform better as they are shrunk, the interconnects perform worse as they get smaller. The resistance and capacitance goes up. So the interconnect problem alone virtually requires that the industry transitions to monolithic 3D.

Question: So 3D solutions greatly reduce the length of the interconnects, thereby eliminating interconnects as a bottleneck?

Yes. the layers will be right on top of each other, thereby minimizing the length of the interconnects. With 2d, the interconnects necessarily need to be made much longer, degrading performance.

Question: How do 3D interconnects affect power consumption and heat dissipation?

3D interconnects substantially reduce power consumption/heat dissipation, because you no longer need to pump as much power through the very long interconnects. There has been considerable research in the semiconductor industry for making interconnects out of carbon nanotubes or graphene, which would be quite difficult to implement. 3D eliminates the need for new materials and research stage technologies.

Question: When many people think of 3d chips, they think of Through-silicon Vias (TSVs). How is monolithic 3D different than TSV?

TSVs essentially involve chip stacking. With TSVs, 50 micron holes are drilled through the silicon in order to insert 6-10 micron wires through them. With monolithic 3D, the interconnects can be made much smaller, as small as 40 nm. These vastly smaller interconnects provide 10,000 times the interconnect density of TSV technology. So TSV is better than using the PCB (Printed Circuit Board), but it essentially is like the hybrid approach. Monolithic 3D provides vertical connectivity compatible to the horizontal connectivity which effectively solves the interconnect problem.

Question: Are there cost advantages to using monolithic 3D?

Monolithic 3D should be easy to build, because it does not require any new materials or processes. Manufacturing wise, it involves using technologies that are already in use. So monolithic 3D should end up offering higher performance and lower cost than TSVs.
See more details in the Blog:

Question: How many layers can be built up using monolithic 3D?

There are no hard and fast limits to the number of layers. The first generation will start with 2 layers. But as the technology matures and experience is gained, the number of layers will increase to 4, 8, and upwards. The layers are so thin that even if we get to 1,000 layers of 3D, it will still be thin enough to resemble a chip more than a cube.

Question: And this technology is manufacturable using current fab tools?

Yes, and that is why this technology is such a game changer. Monolithic 3D does not require any new material or new fab tools – it can be made using existing fab tools in standard fabs, utilizing known and mature semiconductor processes.

Question: So monolithic 3D could be used for logic as well as memory?

Yes, and the eventual goal is to combine memory and logic in a single cube. For memory, one lithography step could be applied to multiple layers with huge cost reduction. So one can imagine a couple of layers being used for logic, and all of the other layers being for memory. This should also allow the industry to reexamine some previously abandoned technologies.

Question: What abandoned technologies are you referring to?

Back in 1980, the computer pioneer Gene Amdahl founded a company called trilogy systems to develop a technology known as wafer scale integration. The underlying concept is to have all the circuitry, both logic and memory, etched onto a single wafer. The advantage of this approach is that both logic and memory can be tightly connected as the whole system is integrated on one device. The idea was abandoned because inevitable defects would render the entire wafer nonfunctional. But monolithic 3D would allow us to use wafer scale integration because we could have multiple layers that would provide redundancy. Print all of the circuitry twice, which is feasible given the short interconnects. So this technology should make wafer scale integration viable.
See more details in our blog title: Monolithic 3D IC Could Increase Circuit Integration by 1,000x

Question: Could this technology be used to make high resolution displays?

Yes. It would be used for a small, high-resolution display utilizing extremely low power, and it could project a large image onto a surface. The technology is low risk because it employs processes that have been in use for decades. So it is simply a matter of getting the right architecture. We envision future cellphones that could project large images onto a wall.

Question: What sort of applications could monolithic 3D enable, once this technology matures?

Monolithic 3D could keep Moore’s law going until 2030. It could allow us to fit “server farms on a chip”, and monolithic 3D may be necessary to create an exascale supercomputer within reasonable power limits. But it could also become an enabling technology for robotics and Artificial General Intelligence (AGI). The human brain is so powerful because it takes full advantage of the 3rd dimension. If we develop monolithic 3D to its full potential, it could usher in the age of truly intelligent machines.

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