Southampton researchers have improved the memristor. how they have pushed the memristor – a simpler and smaller alternative to the transistor, with the capability of altering its resistance and storing multiple memory states – to a new level of performance after experimenting with its component materials. They demonstrated a new memristor technology that can store up to 128 discernible memory states per switch, almost four times more than previously reported.
“Memristors are a key enabling technology for next-generation chips, which need to be highly reconfigurable yet affordable, scalable and energy-efficient.
“At the same time this technology is ideal for developing novel hardware that can learn and adapt autonomously, much like the human brain.”
Traditionally, the processing of data in electronics has relied on integrated circuits (chips) featuring vast numbers of transistors – microscopic switches that control the flow of electrical current by turning it on or off.
Transistors have got smaller and smaller in order to meet the increasing demands of technology, but are now reaching their physical limit, with – for example – the processing chips that power smartphones containing an average of five billion transistors.
Emerging nanoionic memristive devices are considered as the memory technology of the future and have been winning a great deal of attention due to their ability to perform fast and at the expense of low-power and -space requirements. Their full potential is envisioned that can be fulfilled through their capacity to store multiple memory states per cell, which however has been constrained so far by issues affecting the long-term stability of independent states. Here, we introduce and evaluate a multitude of metal-oxide bi-layers and demonstrate the benefits from increased memory stability via multibit memory operation. We propose a programming methodology that allows for operating metal-oxide memristive devices as multibit memory elements with highly packed yet clearly discernible memory states. These states were found to correlate with the transport properties of the introduced barrier layers. We are demonstrating memory cells with up to 6.5 bits of information storage as well as excellent retention and power consumption performance. This paves the way for neuromorphic and non-volatile memory applications.
All devices have been fabricated on 6-inch oxidised silicon wafers (200 nm of thermal SiO2). Initially the bottom electrodes were fabricated using photolithography and electron beam evaporation of titanium (5 nm) and platinum (10 nm) followed by lift-off process in N-Methyl-2-pyrrolidone (NMP). Then, 40 nm of TiO2 were deposited using magnetron sputtering. The Al2O3, Ta2O5, and SiO2 layers (4 nm) were also deposited using magnetron sputtering after negative tone photolithography. The active layer is formed after lift-off in NMP. The 4 nm layers of ZnO, HfO2 and WO3 were synthesised using atomic layer deposition (ALD). After that a positive tone photolithography and ion beam milling processes were used to pattern and etch the active layers. The top electrode was fabricated using photolithography, electron beam evaporation of platinum (10 nm) and lift-off in NMP.