3D FPGA – Field-programmable gate arrays With ASIC densities

NuPGA, presented details about its 3-D FPGA technology Friday (Jan. 29) at the Applied Materials Technical Symposium on 3-D Interconnect in Santa Clara, Calif.

EETimes presents the details

Serial entrepreneur Zvi Or-Bach is touting a three-dimensional field-programmable gate array (FPGA) technology that he claims could achieve the densities of an application specific integrated circuit (ASIC). Last year, Or-Bach applied for a patent with Rice University on a graphite-based memory process for creating reprogrammable memory elements, which NuPGA is now using as anti-fuses for its 3D FPGAs.

NuPGA’s anti-fuses start out as an open circuit but can be reprogrammed to create a low-resistance connection when pulsed with a high voltage. By arranging anti-fuses in a separate layer above logic, they could boost the interconnection density of FPGAs to rival ASICs, according to Or-Bach. The only problem is that the high-voltage programming transistors take up so much room that they negate the density boost. NuPGA claims to have solved that problem by burying the programming transistors in a 3-D “foundation” layer beneath the traditional FPGA circuitry.

NuPGA has also patented its 3-D stacking technique, which it believes holds the promise of simplifying the process of stacking DRAM chips on top of processors.