Graphene computer components holds the possibility of increasing computer speeds into the 1-100 terahertz range. This is a significant advance towards making that and other graphene electronic and computer applications possible.
Graphene is considered to be a promising candidate for future nanoelectronics due to its exceptional electronic properties. Unfortunately, the graphene field-effect transistors (FETs) cannot be turned off effectively due to the absence of a band gap, leading to an on/off current ratio typically around 5 in top-gated graphene FETs. On the other hand, theoretical investigations and optical measurements suggest that a band gap up to a few hundred millielectronvolts can be created by the perpendicular E-field in bilayer graphenes. Although previous carrier transport measurements in bilayer graphene transistors did indicate a gate-induced insulating state at temperatures below 1 K, the electrical (or transport) band gap was estimated to be a few millielectronvolts, and the room temperature on/off current ratio in bilayer graphene FETs remains similar to those in single-layer graphene FETs. Here, for the first time, we report an on/off current ratio of around 100 and 2000 at room temperature and 20 K, respectively, in our dual-gate bilayer graphene FETs. We also measured an electrical band gap of >130 and 80 meV at average electric displacements of 2.2 and 1.3 V nm−1, respectively. This demonstration reveals the great potential of bilayer graphene in applications such as digital electronics, pseudospintronics, terahertz technology, and infrared nanophotonics.
Room temperature on/off current ratio of 100 is by no means the upper limit of the graphene FET.
In summary, we demonstrated a bi-layer graphene transistor with an on/off current ratio of around 100 at room temperature. The transport measurement indicates a Schottky barrier height >65 meV at Dave of 2.2 Vnm-1, corresponding to an electrical (transport) bandgap of >130 meV. At 20 K, a device on/off current ratio of about 2000 is demonstrated at Dave of 1.3 Vnm-1. Revealing of the large electrical bandgap in bi-layer graphene may enable a number of novel nanoelectronic and nanophotonic applications.
The fabrication steps of the dual-gate bi-layer graphene field effect transistor (FET) are described as follows:
1. Identification of bi-layer graphene flakes using optical approach and Raman spectroscopy. The bi-layer graphene flakes in this experiment were purchased from Graphene Industries, Inc.
2. First e-beam lithography and source/drain metallization (Ti/Pd/Au/Ti: 0.5/20/20/5 nm).
3. Second e-beam lithography and patterning of the bi-layer graphene channel.
4. Spin coating of the organic seed layer made from a derivative of polyhydroxystyrene (the polymer NFC 1400-3CP manufactured by JSR Micro, Inc.) for atomic layer deposition (ALD). The layer thickness can be adjusted by spin speed. The dielectric constant of this material is about 2.524.
5. Atomic layer deposition of top gate oxide (HfO2) at T < 2000C. 6. Third e-beam lithography and top gate metallization (Ti/Au: 5/25 nm). Poly methyl methacrylate (PMMA) was used as the e-beam resist in all the processing steps mentioned above. Removal of PMMA was realized using acetone and usually was followed by isopropanol rinse. No specific surface cleaning steps were involved in the processing.
A list of recent Mesoscale and Nanoscale Physics papers in arxiv
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