3D Atomic Quantum Chips and Advance to Eventual Large Scale Quantum Tech

Australia’s New South Wales scientists have adapted single atom technology to build 3D silicon quantum chips – with precise interlayer alignment and highly accurate measurement of spin states. The 3D architecture is considered a major step in the development of a blueprint to build a large-scale quantum computer.

They aligned the different layers in their 3D device with nanometer precision – and showed they could read out qubit states with what’s called ‘single shot’, i.e. within one single measurement, with very high fidelity.

“This 3D device architecture is a significant advancement for atomic qubits in silicon,” says Professor Simmons.

They are still at least a decade away from a large-scale quantum computer, the work of CQC2T remains at the forefront of innovation in this space.

Nature Nanotechnology – Spin read-out in atomic qubits in an all-epitaxial three-dimensional transistor

Abstract

The realization of the surface code for topological error correction is an essential step towards a universal quantum computer. For single-atom qubits in silicon the need to control and read out qubits synchronously and in parallel requires the formation of a two-dimensional array of qubits with control electrodes patterned above and below this qubit layer. This vertical three-dimensional device architecture8 requires the ability to pattern dopants in multiple, vertically separated planes of the silicon crystal with nanometre precision interlayer alignment. Additionally, the dopants must not diffuse or segregate during the silicon encapsulation. Critical components of this architecture—such as nanowires single-atom transistors and single-electron transistors–have been realized on one atomic plane by patterning phosphorus dopants in silicon using scanning tunnelling microscope hydrogen resist lithography. Here, we extend this to three dimensions and demonstrate single-shot spin read-out with 97.9% measurement fidelity of a phosphorus dopant qubit within a vertically gated single-electron transistor with <5 nm interlayer alignment accuracy. Our strategy ensures the formation of a fully crystalline transistor using just two atomic species: phosphorus and silicon.

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